1. Field of the Invention
The present invention relates to the offset calibration, and more particularly to offset calibration in flash analog to digital converters utilized in data storage systems such as, for example, optical disks data storage systems using data channel circuits.
2. Description of Related Art
In many data detection circuits an electrical signal is received from a data storage media, such as a CD-ROM, DVD, or other optical disk, magnetic hard disk, magnetic tape etc. In the case of optical disks, the electrical signal is generated from light that is reflected off an optical disk and converted to electrical pulses. The electrical pulses may then be transmitted to a data detection circuit for further signal processing to recover the data in a useable form. Data detection circuits may also be combined with circuitry for write operations. For example, circuitry for both read and write operations may be combined read/write channel circuits utilized with magnetic hard disks . In contrast, some optical disks are utilized in read only systems and thus the data detection circuit need not be combined with write circuitry. In general both read only and read/write data detection circuits may also include servo circuitry.
Decoding the pulses into a digital sequence can be performed by a simple peak detector in an analog read channel or, as in more recent designs, by using a discrete time sequence detector in a sampled amplitude read channel. Discrete time sequence detectors are preferred over simple analog pulse detectors because they compensate for intersymbol interferences (ISI) and, therefore, can recover pulses recorded at high densities. As a result, discrete time sequence detectors increase the capacity and reliability of the storage system.
There are several well known discrete time sequence detection methods for use in a sampled amplitude read/write channel circuit including discrete time pulse detection (DPD), partial response (PR) with Viterbi detection, partial response maximum likelihood (PRML) sequence detection, decision-feedback equalization (DFE), enhanced decision-feedback equalization (EDFE), and fixed-delay tree-search with decision-feedback (FDTS/DF). When discrete methods are utilized for sampled amplitude read channel systems, an analog to digital converter (ADC) is typically utilized to convert the high frequency data which is contained on disk.
One type of ADC which may be utilized to convert high frequency disk data is a flash ADC. Such an ADC may contain multiple comparators for conversion of the analog data to digital data. In order to accurately convert the high frequency analog data, it is desirable that the comparators exhibit very little electrical variation from ideal operation even in the presence of "offsets". Many sources exist for offsets including mismatch between two devices (for example transistors, resistors, capacitors, etc.) which though intended to be identical, vary to one degree or another due to limitations of fabrication processes.
One approach to compensate for such offsets is to utilize a DC auto-zero operation. FIG. 1 illustrates an example of an auto-zero operation for use with an amplifier of a flash ADC comparator. As shown in FIG. 1, a comparator having input voltages V.sub.in1 and V.sub.in2, differential transistors M.sub.1 and M.sub.2, and outputs V.sub.o1 and V.sub.o2 are provided. In normal operation, switches S.sub.1 and S.sub.2 are connected to V.sub.in1 and V.sub.in2 respectively and switches S.sub.3 and S.sub.4 are open. For auto-zero operation, the switches S.sub.1 and S.sub.2 are connected to V.sub.ref1 and V.sub.ref2 respectively and switches S.sub.3 and S.sub.4 are closed. Control of the switches in this manner during auto-zero operation will bias the capacitive nodes V.sub.o1 and V.sub.o2 with the effect that the amplifier stage is biased such the output voltage (V.sub.o1 -V.sub.o2) is substantially zero with an input voltage differential of V.sub.ref1 -V.sub.ref2
Auto-zero schemes such as described above have disadvantages in that only DC (or static) mismatches are accounted for and dynamic mismatches (from, for example, different parasitic capacitances, differential charge injection from the switches, etc.) are not corrected. Thus, during actual operation of the amplifier (as opposed to a DC auto-zero situation where the inputs are not changing) offsets will still result. Moreover the auto-zero scheme described above does not address the use of comparators having multiple amplifier stages as the DC offset of the first stage may be accounted for, but the offsets of subsequent stages are not corrected.
It is desirable to auto-zero and calibrate the comparators of a flash ADC in a manner so as not to impact the information that the ADC is converting. In magnetic data storage systems, such as magnetic hard disks, auto-zero and calibration operations may occur when the data channel is not in use. For example, magnetic media is generally written in concentric circles divided into sectors on a disk. Servo information is time multiplexed with user data. This allows time periods to take the user data channel or the servo channel off line to perform an auto-zero or calibration operation. In optical storage systems, however, the data is generally stored in a continuous spiral on the disk without a sector break with both user data and servo data frequency mutliplexed within the continuous data stream. Thus, in optical systems the data channel may be in continuous use for long periods of time without a break. In such cases, the ADC generally can not be disabled for auto-zero and calibration operations without disrupting the data stream. In order to provide for periodic calibrations of the ADC comparators, extra (or proxy or replacement) comparators may be provided via a multiplexing scheme such that if N comparators are to be utilized for the data conversion, the ADC will include at least N+1 comparators. Thus, when one comparator is being calibrated another comparator may be multiplexed into the ADC conversion path so that N comparators are still utilized. However, such multiplexing schemes undesirably provide additional circuit complexity and disrupt the comparator array.